NCP1652, NCP1652A
V CC
V CC(on)
V CC(off)
t
OUTA
t
Last OUTB Pulase
OUTB
t
Latch ? Off
V latch(high)
Latch ? Off
V latch(low)
Latch ? Off
t
Figure 70. Relationship Between the Latch ? Off, V CC , OUTA and OUTB
The Latch ? Off pin is clamped at 3.5 V. A 50 m A (typical)
pull ? up current source is always on and a 100 m A (typical)
pull ? down current source is enabled once the Latch ? Off pin
voltage reaches 3.5 V (typical). This effectively clamps the
Latch ? Off pin voltage at 3.5 V. A minimum pull ? up or
pull ? down current of 50 m A is required to overcome the
internal current sources and latch the controller. The
Latch ? Off input features a 50 m s (typical) filter to prevent
latching the controller due to noise or a line surge event.
The startup circuit continues to cycle V CC between
V CC(on) and V CC(off) while the controller is in latch mode.
The controller exits the latch mode once power to the system
is removed and V CC drops below V CC(reset) .
APPLICATION INFORMATION
ON Semiconductor provides an electronic design tool,
facilitate design of the NCP1652 and reduce development
cycle time. The design tool can be downloaded at
www.onsemi.com.
ORDERING INFORMATION
The electronic design tool allows the user to easily
determine most of the system parameters of a single PFC
stage The tool evaluates the power stage as well as the
frequency response of the system.
Device
NCP1652DWR2G
NCP1652DR2G
NCP1652ADR2G
Package
SO ? 20 WB
(Pb ? Free)
SO ? 16
(Pb ? Free)
SO ? 16
(Pb ? Free)
Shipping ?
1000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
32
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